====== Reconfigurable Computing 7.5 ECTS Prüfung 2023-02-14 ======

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===== Meta-Informationen =====
  * Fach: Reconfigurable Computing 7.5ECTS, SS 23
  * Datum: 14.02.2023
  * Prüfungsart: mündlich
  * Prüfer: Teich
  * Note: 1.7

===== Prüfung =====

4 parts:

might be not complete, left out stupid answers and braindead moments :)

=== Intro ===

was asked about the von neumann architecture?
told something i could remember about cpus, was a weird discussion.

then about an ASIC.
whats better about ASICs

is a von neumann cpu also an asic?

where to configurable devices lay in the scale of von neumann and asics?

why whould you use such devices?
possible answers that I gave were:

rapid prototyping
cost
...?

=== Configurable Devices ===

PLD are?

Whats a PLA?

Implement the function a equals b on a PLA.
gave a truth table.
then sketched a PLA and showed how the funktion would be implemented on a PLA

Whats an FPGA?
whats a coarse grained device, and how does it differ to an device made of luts.
bit functions versus word level logic (i suppose something like this)

=== LUTs ===

I was presented a function

```
abd + ~cd + ~a~bd + a
```

how many luts do you need to implement this?

was a bit wonky here, because i didn't a good look at the funktion and was a bit confused

=== Temporal reconfiguration ===

== Full temporal reconfiguration ==

what are the constraints?

told them the 3 principles
forgot about the 4th, but remembered quickly

was shown 2 Partitions, both had constraint violations I needed to identify

== Partial temporal reconfiguration ==

Was shown the example from the lecture.

Where could you place a new module here?

Mark all maximal squares.

there would have been further questions, but we ran out of time.

=== lg & gl ===